1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to the field of synchronising signals within processors having asynchronous logic.
2. Description of the Prior Art
In some circumstances it may be desirable to use more than one clock within a data processor. However, this can produce its own problems of synchronisation of signals passing between the different clock domains. One example of this is in a system which can respond to a WFI or wait for interrupt signal. Such a signal is used to power down at least a portion of a processor during an inactive period and thereby reduce power consumption, the processor being restarted in response to receipt of an interrupt signal.
FIG. 1 schematically shows a processor 10 of the prior art processing such a WFI signals. In such a system it is desirable for the clock (clkin) that clocks the pipeline to be turned off in response to the WFI. The processor 10 has a “standby” output 43 indicative of when the processor enters this low power mode. This clock clkin therefore needs to be separate from the clock (freeclk) that clocks logic 26. Logic 26 comprising a gate 25 that turns the clkin off and on, interrupt processing logic 20 which processes the WFI and receives the interrupt that will restart the processor and synchronisers 30. Clock clk, clocking the pipeline 15 has a clock tree 17 comprising buffers within its feed line operable to insert delays in the line in various places in order to synchronise the clock across the processor. As these buffers consume power it is desirable for the clock passing through them to be turned off in response to the WFI signal. Therefore in order to save power the freeclk does not have buffers and is not synchronised with the clkin. As the freeclk is not synchronised with the clkin synchronisers 30 are needed on the line transmitting the WFI signal to the interrupt processing logic 20 in order to synchronise this signal with respect to the freeclk.
In safety critical applications it may be desirable to run two (or more) processors in parallel, any difference in their outputs being indicative of an error. In such systems it is important that no false errors are generated. In systems using asynchronous logic such as the one described above, it is possible for a false error to be generated due to very slight timing differences in the clocks of the two processors. FIG. 2 shows two processors 40, 50 similar to those illustrated in FIG. 1 operating in parallel. Outputs 45, 55 from the two processors are compared by comparator 70 (which in this example is an exclusive OR gate) and any difference in the two signals generates an error signal.
In the case of a WFI instruction being used in processors 40 and 50 of FIG. 2, a problem can occur due to synchronisation and a false error may result.
FIG. 3 shows a timing diagram illustrating how a slight difference in clock signals clk2-1 and clk2-2 can result in a false error signal when the wait for interrupt signal is received at or near a clock edge. In this figure the clock signals for processor1 40 and for processor2 50 are shown as clk2-1 and clk2-2 respectively. As can be seen, clk2-2 has a slight delay over clk2-1. It should be noted that this is magnified in this figure and would in reality be much less.
In the example shown in FIG. 3, the WFI-now signal is asserted just before the rising edge of clk2-2 but just after the rising edge of clk2-1. Thus, the first synchronisation register of synchroniser 30 does not transition to the new WFI value in clock cycle 2 for async1 but it does for async2. There is therefore a whole clock cycle difference between the two signals WFI-now-s output from the first register X of synchroniser 30 of FIG. 2.
Although the example given relates to WFI instructions, it should be noted that the problem of false errors being generated in processors operating in parallel is one that may arise for any such processors having asynchronous logic.